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Html Tag |
<iframe src="https://ndatasheet.com/datasheet-frame/300/M5M5V5636UG-16" width="300" height="250" frameborder="0" marginwidth="0" marginheight="0" scrolling="no"></iframe> |
Datasheet Info |
DESCRIPTION The M5M5V5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles |