|
Html Tag |
<iframe src="https://ndatasheet.com/datasheet-frame/300/SY89874AU" width="300" height="250" frameborder="0" marginwidth="0" marginheight="0" scrolling="no"></iframe> |
Datasheet Info |
SY89874AU 2.5GHz, Any-In to LVPECL, Programmable Clock Divider/Fanout Buffer with Internal Termination General Description This low-skew, low-jitter |