|
Html Tag |
<iframe src="https://ndatasheet.com/datasheet-frame/300/CVDD" width="300" height="250" frameborder="0" marginwidth="0" marginheight="0" scrolling="no"></iframe> |
Datasheet Info |
&9'' ® Description CVDD is the resistive tie-up to the core VDD bus for all cell inputs. Equivalent Gates ................... 1.0 HDL Syntax Verilog |