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Html Tag |
<iframe src="https://ndatasheet.com/datasheet-frame/300/IS61DDB42M36" width="300" height="250" frameborder="0" marginwidth="0" marginheight="0" scrolling="no"></iframe> |
Datasheet Info |
I7D7D2DMR-bII (2M x 36 & 4M x (Burst o. f 4) CIO 18) Synchronous SRAMs A MAY 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop |